How to Setup the 8-bit Timers – Counter 0 and Counter 2

There are seven registers to each 8-bit timer that you will need to look at. The table below shows both 8-bit Counters and there related registers with descriptions of what each register stands for. Each register handles different aspects of the timer. Below we will go through what they are called and what each register is used for. As you will notice, Counter 0 and Counter 2 registers look very similar. The difference being whether it contains a 0 or a 2. This allows you to easly identify which register belongs to which Counter.

8-bit Timer Registers

8-bit Timer Register Tables For Counter 0 & Counter 2

Looking at registers TCCR0A and TCCR0B, we will start by setting bits, WGM02, WGM01 and WGM00 for Counter 0 and WGM22, WGM21 and WGM20 for Counter 2. These bits are used for setting what is called the Waveform Generation Mode (WGM). The table below shows you each mode that you can set your timer for and which bits you need to set to get the required mode. (Normal is set by default) (PWM Type explaned here http://appusajeev.wordpress.com/2010/09/30/pwm-in-avr/)

Waveform Generation Mode (WGM):

Now that you have picked the WGM mode you want (Normal, CTC, Phase Correct PWM, or Fast PWM), you will need to set the Compare Output Mode using one of the three sets of tables below. By default, it is set to normal port operation.

Compare Output Mode, Using non-PWM Mode (Normal / CTC)

Compare Output Mode, Using Fast PWM Pulse Width Modulation Mode

Compare Output Mode, Using Phase Correct PWM Mode

Note: When not using normal mode, you will need to set the Data Direction Register (DDR) bit corresponding to the Counters output pin you want to use.

Selecting the Speed at Which The Timer Runs At

By default the ATmega168 runs at 8MHz with the system clock. This means that the timer can be updated, up to 8,000,000 times per second. By setting bits CS02, CS01 and CS00 (that are in register TCCR0B for Counter 0), or setting bits CS22, CS21 and CS20 (that are in register TCCR2B for Counter 2), using the table below you can set the clock from off, which is the default setting, to the full 8mHz or slow down this rate with a prescaler.

Clock Speed Selection

Optional Bit Settings

FOC0A / FOC0B Force Output Compare A and B (that are in register TCCR0B – Counter 0)
FOC2A / FOC2B Force Output Compare A and B (that are in register TCCR2B – Counter 2)

The FOC (FOC0A, FOC0B, FOC2A, FOC2B) bits are only active when the Waveform Generation Mode (WGM) is set to a non-PWM setting. However, when operating in PWM mode this bit must be set to zero when TCCR0B / TCCR2B is written to ensure compatibility with future devices. When the FOC bit is set to one, an immediate Compare Match is forced on the Waveform Generation unit. The FOC output is changed according to the settings of the Output Compare Match bits. The FOC bit is implemented as a strobe. Therefore the value present in the Output Compare Match bits determines the effect of the forced compare. A FOC strobe will not generate any interrupt, nor will it clear the timer in Clear Timer on Compare (CTC) mode using Output Compare Register as TOP. The FOC bit is always read as zero.

Timer/Counter Interrupts (Register TIMSK0 / TIMSK2)

OCIE0A / OCIE2A Timer/Counter Output Compare Match Interrupt Enable A
When the OCIE0A / OCIE2A bit is set to one the Timer/Counter Compare Match Interrupt A is enabled. Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs. (When the OCF0A / OCF2A bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)

OCIE0B / OCIE2B Timer/Counter Output Compare Match Interrupt Enable B
When the OCIE0B / OCIE2B bit is set to one, the Timer/Counter Compare Match Interrupt B is enabled. Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs. (When the OCF0B / OCF2B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)

TOIE0 / TOIE2 Timer/Counter Overflow Interrupt Enable
When the TOIE0 / TOIE2 bit is set to one, the Timer/Counter Overflow interrupt is enabled. Once enabled, an interrupt will execute when an overflow in Timer/Counter occurs. (When the TOV0 / TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR0 / TIFR2)

Interrupt Flag Register (Register TIFR0 / TIFR2)

OCF0A / OCF2A Timer/Counter Output Compare Match Flag A
The OCF0A / OCF2A bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0A / OCR2A (Output Compare Register A). OCF0A / OCF2A is cleared by hardware when executing the corresponding interrupt. OCF0A / OCF2A can also be cleared by writing a logic one to the flag.

OCF0B / OCF2B Timer/Counter Output Compare Match Flag B
The OCF0B / OCF2B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B / OCR2B (Output Compare Register B). OCF0B / OCF2B is cleared by hardware when executing the corresponding interrupt. OCF0B / OCF2B can also be cleared by writing a logic one to the flag.

TOV0 / TOV2 Timer/Counter Overflow Flag
The TOV0 / TOV2 bit is set when an overflow occurs in the Timer/Counter. TOV0 / TOV2 is cleared by hardware when executing the corresponding interrupt. TOV0 / TOV2 can also be cleared by writing a logic one to the flag.

Output Compare Registers

Counter 0 has two Output Compare Registers, A (OCR0A) and B (OCR0B). Counter 2 has two Output Compare Registers, A (OCR2A) and B (OCR2B). In each of these registers you set the valve you would like the Counter to generate an interrupt at.

How to Setup the 16-bit Timer – Counter 1

There are thirteen registers to the 16-bit timer that you will need to look at. The table below shows the 16-bit Counter and its related registers with descriptions of what each register stands for. Each register handles different aspects of the timer. Below we will go through what they are called and what each register is used for. As you will notice, Counter 1 looks similar to the 8-bit timer registers.

16-bit Timer Registers

16-bit Timer Register Tables For Counter 1

Looking at registers TCCR1A and TCCR1B, we will start by setting bits, WGM10, WGM11, WGM12, and WGM13. These bits are used for setting what is called the Waveform Generation Mode (WGM). The table below shows you each mode that you can set your 16-bit timer for and which bits you need to set to get the required mode. (Normal is set by default) (PWM Type explaned here http://appusajeev.wordpress.com/2010/09/30/pwm-in-avr/)

Waveform Generation Mode (WGM) 16-bit timer settings

Now that you have picked the WGM mode you want, you will need to set the Compare Output Mode using one of the three sets of tables below. By default, it is set to normal port operation.

Compare Output Mode, non-PWM

Compare Output Mode, Fast PWM

Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM

Note: When not using normal mode, you will need to set the Data Direction Register (DDR) bit corresponding to the Counters output pin you want to use.

Selecting the Speed at Which The Timer Runs At

By default the ATmega168 runs at 8MHz with the system clock. This means that the timer can be updated, up to 8,000,000 times per second. By setting bits CS12, CS11 and CS10 that are in register TCCR1B, using the table below you can set the clock from off, which is the default setting, to the full 8mHz or slow down this rate with a prescaler.

Clock Speed Selection

Optional Bit Settings That are In Register TCCR1B

ICNC1: Input Capture Noise Canceller (Bit 7 of register TCCR1B) Setting this bit to one activates the Input Capture Noise Canceller. When the noise canceller is activated, the input from the Input Capture pin (ICP1 - PB0 of Port B) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles.

ICES1: Input Capture Edge Select (Bit 6 of register TCCR1B) This bit selects which edge on the Input Capture pin (ICP1 - PB0 of Port B) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if enabled. When the ICR1 is used as the TOP value, if set Waveform Generation Mode (mode 8, 10, 12, 14) bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.

FOC1A / FOC1B Force Output Compare A and B (that are in register TCCR1C)

The FOC1A / FOC1B bits are only active when the Waveform Generation Mode (WGM) is set to a non-PWM setting. When writing a logical one to the FOC1A / FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A / OC1B output is changed according to its COM1A1 / COM1B1 bits setting. The FOC1A / FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1A1 / COM1B1 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP.

Timer/Counter Interrupts (Register TIMSK1)

ICIE1 Timer/Counter Input Capture Interrupt Enable When the ICIE1 bit is written to one the Timer/Counter Input Capture interrupt is enabled. Once enabled, an interrupt will execute when the ICF1 Flag, located in TIFR1, is set.

OCIE1A Timer/Counter Output Compare Match Interrupt Enable A When the OCIE1A bit is set to one the Timer/Counter Compare Match Interrupt A is enabled. Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs. (When the OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)

OCIE1B Timer/Counter Output Compare Match Interrupt Enable B When the OCIE1B bit is set to one, the Timer/Counter Compare Match Interrupt B is enabled. Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs. (When the OCF1B bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)

TOIE1 Timer/Counter Overflow Interrupt Enable When the TOIE1 bit is set to one, the Timer/Counter Overflow interrupt is enabled. Once enabled, an interrupt will execute when an overflow in Timer/Counter occurs. (When the TOV1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)

Interrupt Flag Register (Register TIFR1)

ICF1 Timer/Counter Input Capture Flag The ICF1 bit set when a capture event occurs on the ICP1 pin (PB0 of Port B). When the Input Capture Register (ICR1) is set by the Waveform Generation Mode (mode 8, 10, 12, 14) to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. ICF1 can also be cleared by writing a logic one to the flag.

OCF1A Timer/Counter Output Compare Match Flag A The OCF1A bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR1AH & OCR1AL (Output Compare Register A). OCF1A is cleared by hardware when executing the corresponding interrupt. OCF1A can also be cleared by writing a logic one to the flag.

OCF1B Timer/Counter Output Compare Match Flag B The OCF1B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR1BH & OCR1BL (Output Compare Register B). OCF1B is cleared by hardware when executing the corresponding interrupt. OCF1B can also be cleared by writing a logic one to the flag.

TOV1 Timer/Counter Overflow Flag The TOV1 bit is set when an overflow occurs in the Timer/Counter. TOV1 is cleared by hardware when executing the corresponding interrupt. TOV1 can also be cleared by writing a logic one to the flag.

Now For The Software End Of Things

The ISR(vector_name) Macro – ISR stands for Interrupt Service Routine

Timer Counting Speed Table

How fast should the timer count, in relation to the clock speed of the microcontroller (Typically 8 MHz / 20 MHz)

Values for an 8 MHz clock

Values for a 20 MHz clock

8-bit Timer Example - Hardware Controlled

8-bit Timer Example - Software Controlled

#include <avr/io.h>
#include <avr/interrupt.h>

int main(void)
{
	//*****************************************      Setup 8-bit Timer 0      *****************************************//
	TCCR0A = 0b00000010;		// |COM0A1|COM0A0|COM0B1|COM0B0|0|0|WGM01|WGM00|
					// COMA and COMB are set to normal,  OC0A and OC0B are disconnected respectively
					// WGM is set to CTC - Clear Timer on Compare (of OCR0A) Mode#2 = 010

	TCCR0B = 0b00000000;		// |FOC0A|FOC0B|0|0|WGM02|CS02|CS01|CS00|
					// FOC set to default - WGM02 set to 0 - Clock set to off

	TIMSK0 = 0b00000110;		// |0|0|0|0|0|OCIE0B|OCIE0A|TOIE0|
					// Timer Output Compare Match Interrupt A and B are enabled

	TIFR0  = 0b00000000;		// |0|0|0|0|0|OCFOB|OCF0A|TOV0|
					// Flags are set to 0 - Default settings
	
					// IE If running at 1 mhz (1000000 ticks per second), and selection set to 1024.
					// Duration of one timer tick - 1024/1000000 sec = 0.001024
	OCR0A = 244;			// Set to trip every 0.249856 sec (244 * 0.001024) Which is about 0.25sec, 1/4 of a second.
	OCR0B = 122;			// Set to trip every 0.124928 sec (122 * 0.001024) Which is about 0.125sec, 1/8 of a second.

					// We need to set Port B's Data Direction Register for pin PB0 for output.
	DDRB = DDRB | 0b00000001;	// Leave all the other bits alone, just set bit 0 for output

	sei();				// Enables the global registers.
	
	TCCR0B = 0b00000101;		// |FOC0A|FOC0B|0|0|WGM02|CS02|CS01|CS00|
					// Turn On Clock and set speed selection to Clock/1024
    while(1)
    {
    }
}

ISR#TIMER0_COMPA_vect#
{
	PORTB = PORTB & 0b11111110; 	// Turn off pin PB0 on Port B, leave all other bits alone.
}
	
ISR#TIMER0_COMPB_vect)
{
	PORTB = PORTB | 0b00000001; 	// Turn on pin PB0 on Port B, leave all other bits alone.
}

16-bit Timer Example 1 - Software Controlled

16-bit Timer Example 2 - Software Controlled