How to Setup the 16-bit Timer – Counter 1
There are thirteen registers to the 16-bit timer that you will need to look at. The table below shows the 16-bit Counter and its related registers with descriptions of what each register stands for. Each register handles different aspects of the timer. Below we will go through what they are called and what each register is used for. As you will notice, Counter 1 looks similar to the 8-bit timer registers.
16-bit Timer Registers
| Counter 1 | Description |
|---|
| TCCR1A | Timer/Counter Control Register A |
| TCCR1B | Timer/Counter Control Register B |
| TCCR1C | Timer/Counter Control Register C |
| ICR1H | Input Capture Register 1 High |
| ICR1L | Input Capture Register 1 Low |
| TIMSK1 | Timer/Counter Interrupt Mask Register |
| TIFR1 | Timer/Counter Interrupt Flag Register |
| TCNT1H | Timer/Counter Register High (The Timer - High) |
| TCNT1L | Timer/Counter Register Low (The Timer - Low) |
| OCR1AH | Output Compare Register A High |
| OCR1AL | Output Compare Register A Low |
| OCR1BH | Output Compare Register B High |
| OCR1BL | Output Compare Register B Low |
16-bit Timer Register Tables For Counter 1
| TCCR1A | COM1A1 | COM1A0 | COM1B1 | COM1B0 | - | - | WGM11 | WGM10 |
|---|
| Read/Write | R/W | R/W | R/W | R/W | R | R | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores Compare Output settings and 2 of the 4 Waveform Generation Mode settings. |
| TCCR1B | ICNC1 | ICES1 | - | WGM13 | WGM12 | CS12 | CS11 | CS10 |
|---|
| Read/Write | W | W | R | R/W | R/W | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Stores the Input Capture Noise Canceller and Input Capture Edge Select bits,
2 of the 4 Waveform Generation Mode settings, and the Clock Speed Selection settings. |
| TCCR1C | FOC1A | FOC1B | - | - | - | - | - | - |
|---|
| Read/Write | W | W | R | R | R | R | R | R |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores A and B Force Output Compare bits. |
| TIMSK1 | - | - | ICIE1 | - | - | OCIE1B | OCIE1A | TOIE1 |
|---|
| Read/Write | R | R | R/W | R | R | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores the Input Capture Interrupt Enable bit, the Output Compare Match Interrupt Enable A and B bits and the Timer Overflow Interrupt Enable bit |
| TIFR1 | - | - | ICF1 | - | - | OCF1B | OCF1A | TOV1 |
|---|
| Read/Write | R | R | R/W | R | R | R/W | R/W | R/W |
| Initial Value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Stores the Input Capture Flag, the Output Compare Match Flags A and B and the Timer Overflow Interrupt flag |
Looking at registers TCCR1A and TCCR1B, we will start by setting bits, WGM10, WGM11, WGM12, and WGM13. These bits are used for setting what is called the Waveform Generation Mode (WGM). The table below shows you each mode that you can set your 16-bit timer for and which bits you need to set to get the required mode. (Normal is set by default)
(PWM Type explaned here http://appusajeev.wordpress.com/2010/09/30/pwm-in-avr/)
Waveform Generation Mode (WGM) 16-bit timer settings
| Mode | WGM13 | WGM12 | WGM11 | WGM10 | Description | TOP |
|---|
| 0 | 0 | 0 | 0 | 0 | Normal | 0xFFFF |
| 1 | 0 | 0 | 0 | 1 | Pulse Width Modulation (PWM), Phase Correct, 8-bit | 0x00FF |
| 2 | 0 | 0 | 1 | 0 | Pulse Width Modulation (PWM), Phase Correct, 9-bit | 0x01FF |
| 3 | 0 | 0 | 1 | 1 | Pulse Width Modulation (PWM), Phase Correct, 10-bit | 0x03FF |
| 4 | 0 | 1 | 0 | 0 | Clear Timer on Compare (CTC) | OCR1A |
| 5 | 0 | 1 | 0 | 1 | Fast Pulse Width Modulation (PWM), 8-bit | 0x00FF |
| 6 | 0 | 1 | 1 | 0 | Fast Pulse Width Modulation (PWM), 9-bit | 0x01FF |
| 7 | 0 | 1 | 1 | 1 | Fast Pulse Width Modulation (PWM), 10-bit | 0x03FF |
| 8 | 1 | 0 | 0 | 0 | Pulse Width Modulation (PWM), Phase and Frequency Correct | ICR1 |
| 9 | 1 | 0 | 0 | 1 | Pulse Width Modulation (PWM), Phase and Frequency Correct | OCR1A |
| 10 | 1 | 0 | 1 | 0 | Pulse Width Modulation (PWM), Phase Correct | ICR1 |
| 11 | 1 | 0 | 1 | 1 | Pulse Width Modulation (PWM), Phase Correct | OCR1A |
| 12 | 1 | 1 | 0 | 0 | Clear Timer on Compare (CTC) | ICR1 |
| 13 | 1 | 1 | 0 | 1 | (Reserved) | - |
| 14 | 1 | 1 | 1 | 0 | Fast Pulse Width Modulation (PWM) | ICR1 |
| 15 | 1 | 1 | 1 | 1 | Fast Pulse Width Modulation (PWM) | OCR1A |
Now that you have picked the WGM mode you want, you will need to set the Compare Output Mode using one of the three sets of tables below. By default, it is set to normal port operation.
Compare Output Mode, non-PWM
| COM1A1/COM1B1 | COM1A0/COM1B0 | Description |
|---|
| 0 | 0 | Normal port operation, OC1A/OC1B disconnected. |
| 0 | 1 | Toggle OC1A / OC1B on Compare Match. |
| 1 | 0 | Clear OC1A / OC1B on Compare Match (Set output to low level). |
| 1 | 1 | Set OC1A / OC1B on Compare Match (Set output to high level). |
Compare Output Mode, Fast PWM
| COM1A1/COM1B1 | COM1A0/COM1B0 | Description |
|---|
| 0 | 0 | Normal port operation, OC1A/OC1B disconnected. |
| 0 | 1 | WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. |
| 1 | 0 | Clear OC1A/OC1B on Compare Match,set OC1A/OC1B at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC1A/OC1B on Compare Match,clear OC1A/OC1B at BOTTOM (inverting mode) |
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
| COM1A1/COM1B1 | COM1A0/COM1B0 | Description |
|---|
| 0 | 0 | Normal port operation, OC1A/OC1B disconnected. |
| 0 | 1 | WGM13:0 = 9 or 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. |
| 1 | 0 | Clear OC1A/OC1B on Compare Match when up counting.
Set OC1A/OC1B on Compare Match when down counting. |
| 1 | 1 | Set OC1A/OC1B on Compare Match when up counting.
Clear OC1A/OC1B on Compare Match when down counting. |
Note: When not using normal mode, you will need to set the Data Direction Register (DDR) bit corresponding to the Counters output pin you want to use.
| Counter 1 in register TCCR1A |
|---|
| COM1A1 & COM1A0 | COM1B1 & COM1B0 |
| OC1A is PB1 (pin 1 on Port B) | OC1B is PD2 (pin 2 on Port B) |
Selecting the Speed at Which The Timer Runs At
By default the ATmega168 runs at 8MHz with the system clock. This means that the timer can be updated, up to 8,000,000 times per second. By setting bits CS12, CS11 and CS10 that are in register TCCR1B, using the table below you can set the clock from off, which is the default setting, to the full 8mHz or slow down this rate with a prescaler.
Clock Speed Selection
| CS12 | CS11 | CS10 | Description ( Counter 1 ) |
|---|
| 0 | 0 | 0 | No clock source (Timer/Counter stopped) |
| 0 | 0 | 1 | Clock (No prescaling) |
| 0 | 1 | 0 | Clock/8 (From prescaler) |
| 0 | 1 | 1 | Clock/64 (From prescaler) |
| 1 | 0 | 0 | Clock/256 (From prescaler) |
| 1 | 0 | 1 | Clock/1024 (From prescaler) |
| 1 | 1 | 0 | External clock source on T0 pin. Clock on falling edge. |
| 1 | 1 | 1 | External clock source on T0 pin. Clock on rising edge. |
Optional Bit Settings That are In Register TCCR1B
ICNC1: Input Capture Noise Canceller (Bit 7 of register TCCR1B)
Setting this bit to one activates the Input Capture Noise Canceller. When the noise canceller is activated, the input from the Input Capture pin (ICP1 - PB0 of Port B) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles.
ICES1: Input Capture Edge Select (Bit 6 of register TCCR1B)
This bit selects which edge on the Input Capture pin (ICP1 - PB0 of Port B) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if enabled. When the ICR1 is used as the TOP value, if set Waveform Generation Mode (mode 8, 10, 12, 14) bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
FOC1A / FOC1B Force Output Compare A and B (that are in register TCCR1C)
The FOC1A / FOC1B bits are only active when the Waveform Generation Mode (WGM) is set to a non-PWM setting. When writing a logical one to the FOC1A / FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A / OC1B output is changed according to its COM1A1 / COM1B1 bits setting. The FOC1A / FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1A1 / COM1B1 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP.
Timer/Counter Interrupts (Register TIMSK1)
ICIE1 Timer/Counter Input Capture Interrupt Enable
When the ICIE1 bit is written to one the Timer/Counter Input Capture interrupt is enabled. Once enabled, an interrupt will execute when the ICF1 Flag, located in TIFR1, is set.
OCIE1A Timer/Counter Output Compare Match Interrupt Enable A
When the OCIE1A bit is set to one the Timer/Counter Compare Match Interrupt A is enabled.
Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs.
(When the OCF1A bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)
OCIE1B Timer/Counter Output Compare Match Interrupt Enable B
When the OCIE1B bit is set to one, the Timer/Counter Compare Match Interrupt B is enabled.
Once enabled, an interrupt will execute when a Compare Match in Timer/Counter occurs.
(When the OCF1B bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)
TOIE1 Timer/Counter Overflow Interrupt Enable
When the TOIE1 bit is set to one, the Timer/Counter Overflow interrupt is enabled.
Once enabled, an interrupt will execute when an overflow in Timer/Counter occurs.
(When the TOV1 bit is set in the Timer/Counter Interrupt Flag Register – TIFR1)
Interrupt Flag Register (Register TIFR1)
ICF1 Timer/Counter Input Capture Flag
The ICF1 bit set when a capture event occurs on the ICP1 pin (PB0 of Port B). When the Input Capture Register
(ICR1) is set by the Waveform Generation Mode (mode 8, 10, 12, 14) to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. ICF1 can also be cleared by writing a logic one to the flag.
OCF1A Timer/Counter Output Compare Match Flag A
The OCF1A bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR1AH & OCR1AL (Output Compare Register A). OCF1A is cleared by hardware when executing the corresponding interrupt. OCF1A can also be cleared by writing a logic one to the flag.
OCF1B Timer/Counter Output Compare Match Flag B
The OCF1B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR1BH & OCR1BL (Output Compare Register B). OCF1B is cleared by hardware when executing the corresponding interrupt. OCF1B can also be cleared by writing a logic one to the flag.
TOV1 Timer/Counter Overflow Flag
The TOV1 bit is set when an overflow occurs in the Timer/Counter. TOV1 is cleared by hardware when executing the corresponding interrupt. TOV1 can also be cleared by writing a logic one to the flag.
|
